Title:
PARALLEL-SERIAL CONVERTER
Document Type and Number:
Japanese Patent JPH06224781
Kind Code:
A
Abstract:
PURPOSE: To prevent the occurrence of data losses due to mistiming by providing a phase analyzing means which analyzes the phase of input data words of parallel bits in addition to a time base which sets two clock signals having opposite phases. CONSTITUTION: A first clock signal HM times an inputted parallel data word DE at the output of a parallel-parallel register 3. A local time base 1a simultaneously generates two clock signals HM' and the inverse of HM' having nearly opposite phases and a second loading clock signal LOAD so that time dependency may exists among the signals. A phase analyzing circuit 5 sets and outputs a control signal CM for selecting one out of the two clock signals HM' and the inverse of HM' in accordance with the phase shift between the inputted data word DE and the first clock signal H Therefore, a parallel-to- serial converter in which the timing clock signals of the parallel-parallel register 3 and a parallel-serial register 4 mutually rely upon another is obtained and the occurrence of data losses due to mistiming can be prevented.
Inventors:
JIYATSUKU MAJIYOO
ARAN SHIYUMARAN
ARAN SHIYUMARAN
Application Number:
JP20035193A
Publication Date:
August 12, 1994
Filing Date:
July 20, 1993
Export Citation:
Assignee:
CENTRE NAT ETD TELECOMM
International Classes:
H03K5/26; H03M9/00; (IPC1-7): H03M9/00
Attorney, Agent or Firm:
Keiichi Yamamoto