PURPOSE: To obtain a stable output signal without using a delay element adjusting a timing between a data signal and a clock signal.

CONSTITUTION: The converter is provided with a 1st latch 2 latching a data signal entering a data terminal A at a rising of a clock signal entering a clock terminal C, a 2nd latch 3 latching other data signal entering other data terminal B at a trailing of the clock signal, and the clock input terminal C and an inverting amplifier 4 are connected, an output of the 1st latch 2 and an output of the inverting amplifier 4 are connected to one AND input of a two- AND.NOR gate 5 and an output of the 2nd latch 3 and the clock terminal C are connected to the other AND input. Through the constitution above, the effect of the element delay is eliminated and a stable output signal is obtained.