PURPOSE: To provide an image processing parallel storage device with a simple hardware accessible simultaneously with respect to various access forms.
CONSTITUTION: An address calculation circuit section 10 being a component of the parallel storage device calculates address of a corresponding storage module based on access form, reference coordinate and each storage module number. A memory cell 20 makes storage and input output of real data according to the calculated address and input of a read/write signal. An omega network 30 generates a proper path to make an actual processing sequence of the storage module with an AND required by the processor and products an output of data from the memory cell through this path. A shift circuit section 40 generates a proper path between the omega network and a data terminal based on an input command of the access form.
| WO/1997/008610 | AN APPARATUS FOR PERFORMING MULTIPLY-ADD OPERATIONS ON PACKED DATA |
| WO/2006/054099 | COMPUTER SYSTEM MODEL |
| WO/2014/041395 | SYSTEM-ON-CHIP DEVICE, METHOD OF PERIPHERAL ACCESS AND INTEGRATED CIRCUIT |
PARK JONG WON (KR)
KIM GIL YOON (KR)
| JPS60260086A | 1985-12-23 |
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