Title:
PARALLEL TESTING CIRCUIT
Document Type and Number:
Japanese Patent JP2601120
Kind Code:
B2
Abstract:
PURPOSE: To easily cope with plural parallel testing capable of performing the same access-check as that of normal testing time and having a simple construction of circuits and capable of changing the degree of a parallelism at the time of a parallel testing.
CONSTITUTION: Data signals (RWBS 0 to 3 and RD 0 to 3) to be pairs are connected to gate connection points of pull-out transistors for wired NOR contaction points (RD, the inverse of RD) via respective swtiching transistors. The inverted output of RD and the inverse of RD is connected to the gates of a first NAND and the inverted output of the inverse of RD and RD is connected to the gates of a second NAND and their outputs drive the output terminal (D out). At the time of the parallelism testing, a defect is decided while making the output to be a high impedance when the defect presents by making switching transistors giving data signals to be tested at a same time to the RD and the inverse of RD to turn ON.
More Like This:
Inventors:
Matsunori Yoshinori
Application Number:
JP963293A
Publication Date:
April 16, 1997
Filing Date:
January 25, 1993
Export Citation:
Assignee:
NEC
International Classes:
G11C29/00; G11C29/26; G11C29/28; G11C29/34; G11C29/38; (IPC1-7): G11C29/00
Domestic Patent References:
| JP4212799A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)