Title:
PARALLEL TYPE TIME SWITCH
Document Type and Number:
Japanese Patent JP2918007
Kind Code:
B
Abstract:
PURPOSE: To monitor entire signal routes without any omission by the minimum number of time slots, and the minimum kinds of test patterns.
CONSTITUTION: In a time switch which inserts the test patterns into each signal in1-inN (N is an integer more than 2) inputted through the first-Nth signal lines, test patterns A are inserted into the free time slots FTS of the Ist frames (I is the entire number 1-N) of the Ith input signals. Then, the test patterns are read from the free time slots FTS of the Ith frames of the Ist input signals into which the patterns are inserted, and collated. Each time slot FTS is at the same position in each frame into which the test pattern is inserted.
Inventors:
Yamashita, Hiroshi
Application Number:
JP1992000083406
Publication Date:
April 23, 1999
Filing Date:
March 05, 1992
Export Citation:
Assignee:
NEC CORP
International Classes:
H04J3/14; H04L7/00; H04M3/26; H04Q1/24; H04Q3/52; H04Q11/04; H04Q11/06; H04J3/14; H04L7/00; H04M3/26; H04Q1/18; H04Q3/52; H04Q11/04; H04Q11/06; (IPC1-7): H04Q11/04; H04J3/14; H04M3/26; H04Q3/52