PURPOSE: To realize the parallel calculations of the 1st and 2nd vector arithmetic formulas by reading cyclically the input vectors out of the 1st and 2nd memories and at the same time reading cyclically the input vector out of a 3rd memory.

CONSTITUTION: The data are read out of the memories 33a and 33b with use of the cyclic addresses of the address generators 32a and 32b and a read signal R. At the same time, the data is read out of a memory 33c with use of the cyclic address of an address generator 32c and a read signal R0. These data are written with a write signal W0. A multiplier 36a multiplies the data received from data buses 34a and 34b by each other. An arithmetic unit 36a adds the result of multiplication received from a multiplier 35a to the data on a register 37a and writes them into the register 37a. A multiplier 35b multiplies the data received from data buses 34b and 34c, and an arithmetic unit 36b adds the result of multiplication received from the multiplier 35b to the data on a register 37b to write them into the register 37b. Then the data on the register 37b is written into the memory 33c with the signal W0.