Title:
PARALLELLY OPERATED HIGH-SPEED COUNTER
Document Type and Number:
Japanese Patent JP3566342
Kind Code:
B2
Abstract:
PURPOSE: To provide a parallelly operated high-speed counter for making high- speed counting possible by parallelly operating the two counters of two system for the high-speed counting impossible by one counter.
CONSTITUTION: This counter is provided with counter enable input 100, clock input 200, counter enable flip-flops 61-63, a toggle flip-flop 51, even flip-flops 71-73 and a counter increment control circuit 80, an add counter 91 and an even counter 92 for performing an output operation based on a fixed truth table. Odd counter output 400 and even counter output 500 are multiplexed in an MUT (93) and outputted as double-speed counter output 600.
Inventors:
Yosuke Iida
Akihiko Kosuge
Akihiko Kosuge
Application Number:
JP17190894A
Publication Date:
September 15, 2004
Filing Date:
June 30, 1994
Export Citation:
Assignee:
Advantest Corporation
International Classes:
H03K21/00; H03K23/00; G01R31/28; (IPC1-7): H03K23/00; G01R31/28; H03K21/00
Domestic Patent References:
| JP6037628A | ||||
| JP6180685A | ||||
| JP2008248U |
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