PURPOSE: To realize the parity arithmetic circuit ready to start calculation by a data load signal without using any excess clocks concerning the parity arithmetic circuit for serial input data.

CONSTITUTION: A parity arithmetic part 10 is provided to calculate the parity of the input data, a first selection part 20 is provided to switch the output of the parity arithmetic part 10 and the input data, a first latch part 30 is provided to latch the output of the first selection part 20, a second selection part 40 is provided to switch the output of the first latch part 30 and the output of a second latch part 50, and the second latch part 50 is provided to latch the output of the second selection part 40. When calculating the parity of the input data synchronized to the clock, according to the data load signal showing the calculation start to execute the parity calculation, the first latch part 30 is initialized by the first data of the input data, and the parity calculation is started.