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Title:
PARITY CHECK SYSTEM
Document Type and Number:
Japanese Patent JPS5694446
Kind Code:
A
Abstract:

PURPOSE: To use general addition instruction, compare instruction and branch instruction to perform parity check, by adding bits whose balues are 1 to perform data parity check, and by comparing the addition result with the parity bit.

CONSTITUTION: At first, temporary memories which store bit number X and addition result Y are preset to 1 and 0 respectively, and next, it is checked whether contents of the bit indicated by number X is 1 or not; if contents are 1, 1 is added to addition result Y and the result is stored into the memory; and unless contents are 1, control is transferred to the next step, and this operation is repeated for the number of bits. After the prescribed number of number X is compared repeatedly, two bits of addition result Y and the parity bit are compared; if they agree with each other, parity bit OK is output; and if they do not agree, data parity error is output. In case of odd parity, if they don't agree, the parity error is output; and otherwise, parity check OK is output.


Inventors:
YOSHIDA YUKIHIKO
Application Number:
JP17074579A
Publication Date:
July 30, 1981
Filing Date:
December 27, 1979
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
G06F11/10; H03M13/00; (IPC1-7): G06F11/10