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Patent Searching and Data


Title:
PARITY ERROR DETECTING SYSTEM
Document Type and Number:
Japanese Patent JPH02150941
Kind Code:
A
Abstract:

PURPOSE: To decrease the hardware quantity by using a single parity generator to constitute a memory system having a detecting function for the parity error caused by a soft error of the data stored in a memory.

CONSTITUTION: A parity generator 1 produces one bit of an even parity and one bit of an odd parity to the input data of (N + 1) bits with the even and odd numbers of bits obtained with the input data set at H respectively. When the N-bit data are written into the memories 10 and 11, the remaining 1-bit input is set at L and the parity bits are produced and written into both memories 10 and 11. When the data are read out of both memories 10 and 11, the N-bit data and the 1-bit parity are read out and the total (N + 1) bits are inputted to the generator 1. In the case the stored data partly has the inversion of bit and produces a soft error owing to the influence of the cosmic rays, etc., the parity output of an odd or even number which is different from the normal one is obtained. Thus a parity error can be detected.


Inventors:
KURODA KOJI
KUMAGAI SUSUMU
Application Number:
JP1988000304129
Publication Date:
June 11, 1990
Filing Date:
December 02, 1988
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
G06F11/10; G06F12/16; (IPC1-7): G06F11/10; G06F12/16