PURPOSE: To avoid a parity circuit from being made huge and to attain parity calculation at a low speed by using a low speed signal before scrambling inputted to a 1st parity calculation circuit so as to correct the parity of a high speed signal after scrambling and inserting the corrected parity.

CONSTITUTION: The parity generating circuit is provided with a 1st parity calculation circuit 6 having a 3rd exclusive OR(3rd EOR) circuit 614 correcting an output of a flip-flop(FF) circuit 613 in response to an even number or an odd number of "1s" in one frame of a pseudo random signal outputted from a pattern generator 512. Then the parity of a high speed signal after scramble is corrected and inserted by using a low speed signal before scramble inputted to a 1st parity calculation circuit 6. Thus, the parity generating circuit is realized, in which the circuit scale is not made huge and the parity calculation is enabled.