Title:
分周回路
Document Type and Number:
Japanese Patent JP4780144
Kind Code:
B2
Abstract:
Circuits and methods and for dividing a frequency of an input signal by an integer divider value. The circuit generally comprises (a) a first frequency divider, including a first plurality of serially connected delay elements receiving the input signal and a first configurable feedback network, (b) a second frequency divider, including a second plurality of serially connected delay elements receiving an inverse of the input signal and a second configurable feedback network (c) configurable logic configured to select and/or combine outputs of the first and second frequency dividers and to produce a frequency divided output signal, and (d) a programmable circuit configured to selectably configure the first and second configurable feedback networks and the configurable logic. The present invention advantageously provides for a frequency divider structure that can be easily programmed to provide any integer divide ratio with a 50% duty cycle.
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Inventors:
Jeremy Scutelli
Application Number:
JP2008137661A
Publication Date:
September 28, 2011
Filing Date:
May 27, 2008
Export Citation:
Assignee:
Seiko Epson Corporation
International Classes:
H03K23/64; H03K21/00; H03K23/66; H03L7/06; H03L7/08
Domestic Patent References:
| JP7154243A | ||||
| JP8340250A | ||||
| JP10135821A | ||||
| JP10276083A | ||||
| JP54112152A | ||||
| JP200243929A |
Attorney, Agent or Firm:
Masahiko Ueyanagi
Osamu Suzawa
Kazuhiko Miyasaka
Osamu Suzawa
Kazuhiko Miyasaka