Title:
分周回路
Document Type and Number:
Japanese Patent JP5873543
Kind Code:
B2
Abstract:
A divider circuit includes a shift register which generates 2X (X is a natural number greater than or equal to 2) pulse signals in accordance with a first clock signal or a second clock signal and outputs them, and a divided signal output circuit which generates a signal to be a third clock signal with a cycle X times longer than a cycle of the first clock signal in accordance with the 2X pulse signals and outputs it. The divided signal output circuit includes X first transistors which control whether voltage of the signal to be the third clock signal is set to first voltage; and X second transistors which control whether voltage of the signal to be the third clock signal is set to second voltage.
Inventors:
Kei Takahashi
Yoshiaki Ito
Yoshiaki Ito
Application Number:
JP2014211540A
Publication Date:
March 01, 2016
Filing Date:
October 16, 2014
Export Citation:
Assignee:
Semiconductor Energy Laboratory Co., Ltd.
International Classes:
H03K23/44; H01L29/786
Domestic Patent References:
| JP2010049791A | ||||
| JP2008122939A | ||||
| JP2004226429A |