Title:
PARTIALLY READABLE/WRITABLE RECONFIGURABLE SYSTOLIC ARRAY SYSTEM AND METHOD
Document Type and Number:
Japanese Patent JP2021108104
Kind Code:
A
Abstract:
To provide a data processing system that includes a reconfigurable systolic array circuit.SOLUTION: A reconfigurable systolic array circuit 700 includes a first circuit block 712 containing one or more groups of processing elements and a second circuit block 714 containing one or more groups of processing elements. The reconfigurable systolic array circuit further includes a first bias adder 742 containing a cumulative circuit that adds a matrix bias to a cumulative value, a multiplication product, or a combination thereof. The reconfigurable systolic array circuit further includes a first routing circuit 728 that routes a derivative from a first circuit block to a second circuit block, from the first circuit block to a first bias addition with a cumulative circuit or to the combination thereof.SELECTED DRAWING: Figure 7
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Inventors:
KAMLESH R PILLAI
GURPREET SINGH KALSI
CHRISTOPHER JUSTIN HUGHES
GURPREET SINGH KALSI
CHRISTOPHER JUSTIN HUGHES
Application Number:
JP2020157941A
Publication Date:
July 29, 2021
Filing Date:
September 18, 2020
Export Citation:
Assignee:
INTEL CORP
International Classes:
G06F17/16; G06F15/80; G06N3/063
Attorney, Agent or Firm:
Longhua International Patent Service Corporation