Title:
PASSIVE UNIT COUNTING INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JP2843461
Kind Code:
B2
Abstract:
PURPOSE: To surely eliminate a low-order rank level when a card is successively used by performing a write operation by the case of a high-order rank level every time all the cases of the low-order rank level are activated and eliminating the case of a low-order level from it.
CONSTITUTION: A ghost level is selectively address specifiable so as to decide the contents by supplying address signals to respective address lines A21 and A22 or by appropriately increasing a column decoder 2. The specified address specification of the ghost level is possible only when a write or elimination phase is not achieved due to two false inputs connected to the write and elimination lines of an AND gate 45. However, when the gap of the write phase and a row 11 are specified by an address A11, the row 11 is specified by the address A11 in the AND gate 33 and the row 21 is address specified in the AND gate 44 activated in the write line W and the address A11.
Inventors:
EITSUKU DEPURE
ROORAN SUURUJAN
ROORAN SUURUJAN
Application Number:
JP15955492A
Publication Date:
January 06, 1999
Filing Date:
June 18, 1992
Export Citation:
Assignee:
SANTORU NASHIONARU DECHUUDO DE TEREKOMYUNIKASHION
RA HOSUTO
ESU TEE MIKUROEREKUTORONIKUSU SA
RA HOSUTO
ESU TEE MIKUROEREKUTORONIKUSU SA
International Classes:
G11C17/00; G06F12/16; G06K19/07; G07F7/08; G07F7/10; G11C16/02; G11C16/10; H03K21/00; (IPC1-7): G06K19/07; G06F12/16; G11C16/02; H03K21/00
Domestic Patent References:
| JP63136295A | ||||
| JP3188541A | ||||
| JP6059454A |
Attorney, Agent or Firm:
Hisami Fukami (4 outside)