Title:
PATTERN DISPOSED WITH RECESS BY ANISOTROPIC REACTIVE ION ETCHING AND HIGH DENSITY MULTILAYER METALLIZED INTEGRATED CIRCUIT DESIGNED THEREBY
Document Type and Number:
Japanese Patent JPS6074456
Kind Code:
A
Abstract:
An integrated circuit having a plurality of devices on a substrate is disclosed, wherein a plurality of metallization layers, separated by a plurality of insulating layers, are used to interconnect the devices. Each metallization layer is recessed in an upper portion of a corresponding dielectric layer. A metallization layer is connected to a lower one, or, in the case of the first metallization layer, to the devices, by solid contacts extending through via windows in the lower portion of the corresponding dielectric layer.A method of manufacturing such an integrated circuit is also disclosed, whereby each layer is formed in two steps. First, the lower portion of the insulating layer is deposited, the contact pattern opened and the vias windows filled with metal to provide contacts even with the top surface of the lower portion of the insulating layer. Then, the upper portion of the insulating layer is deposited overthe lower portion, the metallization pattern opened, and the pattern filled with metal up to and even with the top surface of the upper portion of the insulating layer. The metal filling step is produced by depositing a metal layer over the corresponding portion of opened insulating layer, masking the opened regions and selectively and directionally removing the unprotected metal layer.
Inventors:
ANDORIYUU ERU UU
Application Number:
JP12430284A
Publication Date:
April 26, 1985
Filing Date:
June 16, 1984
Export Citation:
Assignee:
DIGITAL EQUIPMENT CORP
International Classes:
H01L21/302; H01L21/3065; H01L21/3205; H01L21/768; H01L23/52; H01L23/528; (IPC1-7): H01L21/302; H01L21/88
Domestic Patent References:
| JPS58155A | 1983-01-05 |
Attorney, Agent or Firm:
Minoru Nakamura