To obtain a small-sized and inexpensive circuit that generates a frame pattern for a test device for high-speed data communication.

This pattern generating circuit 1 consists of a counter 2, a low-speed RAM 3, a counter 4, a high-speed RAM 5, a PN generator 6, and switches 7, 8, 9, and the switches 7, 8, 9 are switched in response to the level of an input signal 10, the high-speed RAM 5 stores data relating to an SOH stored in the low speed RAM 3, data relating to the SOH stored in the high- speed RAM 5 and random data relating to a payload generated by the PN generator 6 are continuously outputted for each line of SDH frames to generates SDH frames, and the result is outputted as an output signal 11.