Title:
PATTERN GENERATING DEVICE
Document Type and Number:
Japanese Patent JP3150611
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To enable the generation of addresses of different pattern formats by more than one test pattern corresponding to different models of testers by providing the instruction decode of an address generator with general versality.
SOLUTION: This pattern generating device is provided with an address pointer 2 which supplys an instruction memory 1 with a memory address 3, more than one decoders 41 and 42 which are selected by a decode enable signal 22 in order to generate instruction elements 5 corresponding to instruction codes 1-m from the instruction memory 1, and an address generator 6 which generates a branch address 7 corresponding to the instruction elements 5 and sets the branch address 7 to the address pointer 2. By means that the decode enable signal selects the decoders 41 and 42, a cyclic operation is activated and varied kinds of patterns are sequentially generated.
Inventors:
Yoshiaki Odashiro
Application Number:
JP7643596A
Publication Date:
March 26, 2001
Filing Date:
March 29, 1996
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
G01R31/28; G01R31/3181; G06F11/22; G01R31/3183; (IPC1-7): G01R31/3183; G06F11/22
Domestic Patent References:
| JP4161869A | ||||
| JP57150200A | ||||
| JP6095369A | ||||
| JP60233742A |
Attorney, Agent or Firm:
Kazuo Sato (3 others)
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