Title:
PATTERN VERIFICATION METHOD, PROGRAM THEREFOR, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP2007057948
Kind Code:
A
Abstract:
To provide a pattern verifying method capable of shortening TAT (Turn Around Time).
The verification method for a semiconductor integrated circuit pattern includes: a step of extracting a pattern equal to or smaller than a specified pattern dimension; a step of extracting a pattern edge to be an object for lithography simulation from the above extracted pattern; and a step of subjecting the extracted pattern edge to the simulation to verify the pattern.
Inventors:
OGAWA RYUJI
HASHIMOTO KOJI
HASHIMOTO KOJI
Application Number:
JP2005244448A
Publication Date:
March 08, 2007
Filing Date:
August 25, 2005
Export Citation:
Assignee:
TOSHIBA CORP
International Classes:
G03F1/36; G03F1/68; G03F1/70; H01L21/027; H01L21/82
Domestic Patent References:
| JP2001133956A | 2001-05-18 | |||
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| JPH10104818A | 1998-04-24 | |||
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Attorney, Agent or Firm:
Takehiko Suzue
Satoshi Kono
Makoto Nakamura
Kurata Masatoshi
Takashi Mine
Yoshihiro Fukuhara
Sadao Muramatsu
Ryo Hashimoto
Satoshi Kono
Makoto Nakamura
Kurata Masatoshi
Takashi Mine
Yoshihiro Fukuhara
Sadao Muramatsu
Ryo Hashimoto
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