To provide a peripheral component interconnect(PCI) bus trace circuit with which a PCI bus can be observed without requiring any special measuring instrument and the factor of an error occurring on the PCI bus can be observed.

A PCI bus analytic circuit 2 analyzes all transactions to occur on a PCI bus 101 and holds address and commands for preserving the transactions when any error occurs and these held data are sent to a write circuit 3. At the same the, the error detected on the PCI bus 100 is reported to an error detecting circuit 6. When the error report is received, the error detecting circuit 6 sends its factor to the write circuit 3. The write circuit 3 writes data from the PCI bus analytic circuit 2 and error detecting circuit 6 into a RAM 5. A read circuit 4 reads data in the RAM in the entry designated through a system bus 200 and sends them onto the system bus 200.