PURPOSE: To make it possible to detect and correct a code error easily by enabling a memory circuit to correct the code error with data bits synchronized with check bits.
CONSTITUTION: In recording, signal Sj with stereophonic left signal L, right signal R and lst check code P arranged in sequence is inputted to shift register 120 through changeover switch 121. Each data is parallel-converted and then written separately in RAM 110 and RAM 111. Address counter circuit 160 supplies addresses to RAMs 110 and 111 so that respective data L, R and P will be interleaved on memories at constant intervals. Adder 150 adds a fixed value to a read address. In reproduction, signal Si after a check on the existence of a code error is inputted to shift register 120 and written in RAMs 110 and 111. At the time of a read from memories, data in RAM 111 is read out being advanced by a fixed number of words by adder 150.
WADA RIYOUICHI
TSUCHIYA MITSUHARU
ODAGI KANJI
