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Patent Searching and Data


Title:
PEAK DETECTING CIRCUIT
Document Type and Number:
Japanese Patent JPS59122001
Kind Code:
A
Abstract:

PURPOSE: To simplify the constitution of a circuit which suits to IC implementation and performs full-wave rectification by providing the 1st and the 2nd transistors (TR), the 1st and the 2nd load resistances, and a constant current source.

CONSTITUTION: A TRQ21 is connected to a terminal 21 at the base, to a power source VCC at the collector through a load resistance R21, and to the emitter of a TRQ22 at the emitter through a resistance R22. The TRQ22 is connected to a terminal 22 at the base and to the power source VCC at the collector through a load resistance R23 and grounded at the emitter through a constant current source I21. The collectors of the TRs Q21 and Q22 are connected to the minus and plus input terminals of an amplifier circuit 11, and bias voltages having the same level are applied to the bases from the terminals 21 and 22. Further, a detection input signal S1 is supplied to the base of the TRQ21 from the terminal 21. Consequently, the constitution of the circuit which suits to IC implementation and performs fullwave rectification is simplified.


Inventors:
KOUNO MITSUKUMO
Application Number:
JP23400882A
Publication Date:
July 14, 1984
Filing Date:
December 27, 1982
Export Citation:
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Assignee:
TOSHIBA KK
International Classes:
H03G3/30; H03D1/00; H03D1/18; H03G3/20; (IPC1-7): H03D1/00; H03G3/20
Attorney, Agent or Firm:
Takehiko Suzue