Title:
PEAK DETECTION CIRCUIT
Document Type and Number:
Japanese Patent JP2005057627
Kind Code:
A
Abstract:
To provide a peak detection circuit which is highly accurately operated at ultra high speed.
The peak detection circuit is provided with; a transistor 2 having the gate connected to an input terminal 1; a first capacity 3 connected to the source of the transistor; a first switch 4 connected in parallel to the first capacity 3; a buffer circuit to which a voltage held in the first capacity 3 is inputted; a second capacity 6 connected between the output of the buffer circuit 5 and an output terminal 8; and a second switch 7 connected between an input terminal 1 and the output terminal 8.
Inventors:
KIMURA HIROSHI
Application Number:
JP2003288631A
Publication Date:
March 03, 2005
Filing Date:
August 07, 2003
Export Citation:
Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
G01R19/04; H03K5/1532; H04B10/07; H04B10/40; H04B10/50; H04B10/60; H04B10/69; (IPC1-7): H03K5/1532; G01R19/04
Attorney, Agent or Firm:
Hiroshi Maeda
Hiroshi Koyama
Hiroshi Takeuchi
Yuji Takeuchi
Katsumi Imae
Tomoo Harada
Hiroshi Koyama
Hiroshi Takeuchi
Yuji Takeuchi
Katsumi Imae
Tomoo Harada
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