Title:
PEAK DETECTION CIRCUIT
Document Type and Number:
Japanese Patent JP2607425
Kind Code:
B
Abstract:
PURPOSE: To obtain a precise peak detection result of an input signal from a second peak holding circuit by providing the second peak holding circuit for accumulating the maximum value of an output signal of a differential amplifier apart from a first peak holding circuit.
CONSTITUTION: A differential amplifier 10 produces an output signal AMPOUT which responds to a difference between return signals from an analog input signal IN and an active peak holding circuit 12. Accumulation capacitors of the circuit 12 and a passive peak holding circuit 14 monitor the signal AMPOUT and accumulate the maximum value which responds to peak amplitude of the signal AMPOUT while a disable signal DIS is passive. The circuit 12 supplies the return signals, which are indicated as the maximum value, to the amplifier 10. When the circuit 14 supplies the maximum value signal MAX to a voltage follower stage 16 and next a reading enabling signal RBEN is active, its maximum value signal is supplied to the output terminal of the whole circuit. The signal RBEN and a signal RESET become active only while the signal DIS is active.
Inventors:
Suteiibun, Kee Sariban
Jiyosefu, Aaru Piitaa
Jiyosefu, Aaru Piitaa
Application Number:
JP1993000341544
Publication Date:
February 13, 1997
Filing Date:
December 10, 1993
Export Citation:
Assignee:
SONY TEKTRONIX CORP
International Classes:
G01R19/04; H03K5/1532; (IPC1-7): G01R19/04
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