Title:
PEAK HOLD CIRCUIT, SOLID STATE IMAGING DEVICE EMPLOYING IT AND CAMERA MOUNTING IT
Document Type and Number:
Japanese Patent JPH0935492
Kind Code:
A
Abstract:
To obtain a peak hold circuit in which the peak value of an input signal can be detected in a specified section.
The peak hold circuit comprises a section 16 for detecting and holding the peak value of a specific input signal, a switch section 13 provided on the prestage of peak detecting section 16 in order to feed an input signal selectively thereto, and a peak hold control section 15 for controlling the switching section 13 by setting a peak hold section for the input signal.
Inventors:
YOSHIDA SHINYA
MAKI YASUTO
MAKI YASUTO
Application Number:
JP18126095A
Publication Date:
February 07, 1997
Filing Date:
July 18, 1995
Export Citation:
Assignee:
SONY CORP
International Classes:
G01R19/04; G02B7/28; G03B13/36; G11C27/00; H03K5/1532; H04N5/232; H04N5/235; (IPC1-7): G11C27/00; G01R19/04; G02B7/28; G03B13/36; H03K5/1532
Attorney, Agent or Firm:
Kuninori Funabashi