PURPOSE: To improve fast responsiveness by the minimum increment of circuit scale by switching two pairs of peak hold synchronizing with a peak hold instruction signal, and discharging a capacitor for peak hold while a non- selection state is set.

CONSTITUTION: 1/2 frequency division output Q, Q are generated by inputting the peak hold(PH) instruction signal 4 to a DF/F. When the output Q, Q are set at L and H levels respectively, transistors(TR) Q1, Q3 are turned on, and a TR Q2 is turned off, and the selection state of PH of a diode(D) 2 and a capacitor(C) 1 is set. At this time, TRs Q4, Q6 are turned off, and the PH of the D2 and the C2 are set at the non-selection states, and a TR Q5 is turned on, then, the C2 is discharged. Meanwhile, when the output Q, Q are set at H and L levels, the TRs Q4, Q6 are turned on, and the TR Q5 is turned off, then, the selection states of PH of the D2 and the C2 are set, and the TR Q2 is turned on. then, the C1 is discharged. Thereby, it is possible to improve the fast responsiveness by the minimum increment of the circuit scale.