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Title:
PEAK SUPPRESSION CIRCUIT, AND RADIO TRANSMITTER
Document Type and Number:
Japanese Patent JP2012161086
Kind Code:
A
Abstract:

To suppress the peak of an orthogonal multiplex transmission signal, deterioration in quality of which is little for the processing results of a received signal.

The peak suppression circuit which suppresses the peak of an orthogonal multiplex signal, orthogonality of which is guaranteed by a certain time unit, comprises: a detection unit which detects the peak of the orthogonal multiplex signal; a symbol timing detection unit which acquires the symbol timing of the orthogonal multiplex signal; a synthesis unit which generates a peak cancel waveform based on the peak of the orthogonal multiplex signal thus detected and the symbol timing thus acquired; and a removing unit which removes the peak of the orthogonal multiplex signal from the orthogonal multiplex signal by using the peak cancel waveform thus generated. The synthesis unit generates the peak cancel waveform every time unit of the orthogonal multiplex signal.


Inventors:
YANO TAKASHI
HAYASE SHIGENORI
NAITO MASASHI
Application Number:
JP2012083535A
Publication Date:
August 23, 2012
Filing Date:
April 02, 2012
Export Citation:
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Assignee:
HITACHI INT ELECTRIC INC
International Classes:
H04J11/00
Domestic Patent References:
JP2007180666A2007-07-12
JP2003298549A2003-10-17
Foreign References:
WO2007091434A12007-08-16
Attorney, Agent or Firm:
Masahiro Fujii
Masaki Goto