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Title:
PERIOD PROCESSING METHOD USING PLURAL PROCESSORS
Document Type and Number:
Japanese Patent JPH07141300
Kind Code:
A
Abstract:

PURPOSE: To provide a decentralized period processing method using plural processors.

CONSTITUTION: When an in-period-process flag IMF in a period process support circuit 2 is OFF and a flag for interruption generation is ON, processors P1 to Pn are interrupted and a period control program is started at the same time. A period control program places the processors in decentralized execution of the period process program by using a time-out signal holding flag 22 which holds the time-out signal of a timer 21, a period process execution inhibition display flag 27 which is fired by software at the end of the dispatching (actuation end) of all period process object programs to be processed in respective period and reset when a next period comes and the period processes in the last period are all completed, a period process end display flag 28 which indicates that the execution of all the period process object programs to be processed in the respective periods ends, and the period process program and a correspondence table 35 of its execution time in a main storage device 3.


Inventors:
ISHIKAWA EIJI
MATSUDA TOMOSHI
AOKI MICHIHIRO
MIKI SHUJI
HOSHIAI TAKANARI
WATABE NOBUYUKI
Application Number:
JP28910593A
Publication Date:
June 02, 1995
Filing Date:
November 18, 1993
Export Citation:
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Assignee:
NIPPON TELEGRAPH & TELEPHONE
International Classes:
G06F9/46; G06F9/52; G06F9/48; G06F15/16; (IPC1-7): G06F15/16; G06F9/46
Attorney, Agent or Firm:
Masatoshi Isomura