Title:
PERIPHERAL CONTROL UNIT
Document Type and Number:
Japanese Patent JPS5745625
Kind Code:
A
Abstract:
A peripheral device address assignment mechanism is described which does not require the use of plugboards or jumpers. This mechanism enables a host processor to select any desired peripheral device and set its device address to any desired value at any desired time. This is accomplished by providing each peripheral device control unit with a loadable device address register for holding the device address assigned to its peripheral device. Each device control unit is further provided with circuitry responsive to the appearance of a unique I/O command on the processor I/O bus and to the activation of a unique set of the I/O bus data lines by the processor for loading into its device address register the desired device address value as supplied thereto by the processor via the I/O bus.
Inventors:
DAGURASU ROODERITSUKU CHIIZAMU
HOBAATO RAMORII KAATSU JIYUNIA
HOBAATO RAMORII KAATSU JIYUNIA
Application Number:
JP10346281A
Publication Date:
March 15, 1982
Filing Date:
July 03, 1981
Export Citation:
Assignee:
IBM
International Classes:
G06F12/02; G06F13/14; G06F12/06; (IPC1-7): G06F3/00