To freely manage the communication connection to a host device.
When a VBUS line (the output of a buffer 70) of a USB cable 30 is changed or key entry is executed, a port control circuit 62 checks whether the VBUS line is a high(H) level or not. When the VBUS line is turned to H, a CPU 50 allows a clock oscillation/control circuit 66 to increase clock frequency, turns a sleep mode to an operation mode and starts clock supply to an SIE circuit 46 and an EPC circuit 48 to prepare USB communication. The circuit 62 impresses prescribed voltage to a pull-up resistor 78 to pull up D+ line. Therefore a host PC10 recognizes that peripheral equipment 40 is connected to a USB bus. The equipment 40 suitably communicates with the host PC10 in accordance with a request from the PC10. When there is no access for fixed time, the equipment 40 informs the host PC10 of communication end. Therefore the circuit 62 turns voltage to be impressed to the resistor 78 to a low(L) level or HiZ. Then the mode is turned to the sleep mode of low clock frequency.
AIZAWA TAKASHI
KOIDE YUJI
