Title:
PHASE ADJUSTABLE PROGRAMMABLE FREQUENCY TIMING GENERATOR
Document Type and Number:
Japanese Patent JP2754170
Kind Code:
B2
Abstract:
PURPOSE: To reduce jitters by providing a counter for counting an input clock number in the high phase and low phase of output clocks and adjusting the length of the phases while keeping fixed relation with input clocks.
CONSTITUTION: The output clocks are provided with a programmable frequency and a duty cycle so as to provide the respective sets of the prescribed number of output clock cycles with the same length and to provide the respectively corresponding high phase and low phase. Then, An input clock cycle required for the high phase and the low phase is set by a control logic means 51, an input clock cycle number is counted for each high phase in a high phase clock counter 11 and the input clock cycle number is counted for each low phase in a low phase counter 13. Then, the prescribed high phase in the output clock cycle is adjusted by increasing and decreasing the input clock cycle for the length by a phase adjustment means 55.
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Inventors:
KAARU EFU RIIHOORUDO
Application Number:
JP24082694A
Publication Date:
May 20, 1998
Filing Date:
September 09, 1994
Export Citation:
Assignee:
INTERU CORP
International Classes:
G06F1/025; H03K3/64; H03K21/00; H03L7/06; H03L7/00; (IPC1-7): H03L7/00; H03K3/64; H03K21/00
Domestic Patent References:
JP58182924A | ||||
JP5684028A |
Attorney, Agent or Firm:
Masaki Yamakawa
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