Title:
PHASE COMPARATOR CIRCUIT AND SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP3865749
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a phase comparator circuit wherein phase synchronism judgement accuracy is improved, and a semiconductor device comprising the same.
SOLUTION: A pMOS transistor 31 and two nMOS transistors 32, 33 are connected in series between power supply wires, an edge of a reference clock HCLK is detected by a circuit 34, and a signal *DWN of a negative pulse is outputted and supplied to a gate of the pMOS transistor 31. A next edge of a reference clock Hψn is detected, a positive pulse is outputted and supplied to a gate of the nMOS transistor 33, and a signal resulting from inverting a logical value of a generated clock in a circuit 35 is supplied to a gate of the nMOS transistor 32.
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Inventors:
Kotaro Goto
Wakayama Shigetoshi
Wakayama Shigetoshi
Application Number:
JP2005003733A
Publication Date:
January 10, 2007
Filing Date:
January 11, 2005
Export Citation:
Assignee:
富士通株式会社
International Classes:
H03K5/26; H03L7/085; H03L7/081; (IPC1-7): H03L7/085; H03K5/26; H03L7/081
Domestic Patent References:
JP7273645A |
Attorney, Agent or Firm:
Shinkichi Matsumoto
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