To provide a phase comparator in which clocks and data are stably and accurately identified and reproduced regardless of coincidence of presence setup distribution between a rising change phase of an input data signal and its falling change phase.

A phase comparator 101 is provided with AND circuits 21 and 22 for inputting logical signals outputted from latch circuits 13 and 15 and inverted logical signals thereof from a pair of input terminals and outputting the AND result from an output terminal for performing logical operation by combining the rising change point compared result and the falling change point compared result of an input data signal DIN outputted from the latch circuits 13 and 15 to compare the rising change phase and the falling change phase of the input data signal DIN in latch circuits 11-15 for outputting the result of latching a signal from one input terminal into logical state "1" or "0" with a change point of a signal from the other input terminal from the output terminal.