Title:
PHASE COMPARATOR
Document Type and Number:
Japanese Patent JP3215149
Kind Code:
B2
Abstract:
PURPOSE: To obtain a phase comparison characteristic without a dead band by generating a phase lag signal and a phase lead signal whose level is a level of a degree activating a circuit of a next stage even in the steady-state.
CONSTITUTION: An output of an AND gate 3 receiving a reference signal Ref is inputted to a delay circuit 5, and a reference signal dRef delayed thereat becomes a reset input of a latch circuit 9 propagating a phase lead signal DCHG with a control signal RD and a flip-flop circuit 10 via a NOR gate 6. A reset input to a flip-flop circuit 4 propagating the phase lead signal DCHG with the reference signal Ref becomes a control signal RD via a NOR gate 12. An output of an OR gate 14 receiving the control signal from an OR gate 13 receiving an output of the flip-flop circuits 4, 10 becomes a reset input to the flip-flop circuit 2 receiving an armed signal. The armed signal is outputted from the flip-flop circuit 2 and becomes one input to AND gates 3, 8 receiving the signals Ref, RD.
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Inventors:
Minoru Kamada
Masao Kaizuka
Masao Kaizuka
Application Number:
JP6684892A
Publication Date:
October 02, 2001
Filing Date:
March 25, 1992
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
H03K5/26; H03L7/085; H03L7/089; (IPC1-7): H03L7/089; H03K5/26
Domestic Patent References:
| JP435522A |
Attorney, Agent or Firm:
Takehiko Suzue