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Title:
PHASE COMPARATOR
Document Type and Number:
Japanese Patent JP3228414
Kind Code:
B2
Abstract:

PROBLEM TO BE SOLVED: To provide a phase comparator which makes it difficult to generate a dead zone in error detection characteristics, even if an error detection range varies relatively.
SOLUTION: Error signals UPB and DWB are varied in level with a reference signal REF and a comparison signal IN inputted to NAND circuits 11 and 21 and NAND circuits 14 and 24 constituting reset circuits output reset signals at slower falls of the reference signal REF and comparison signal IN. When the comparison signal IN rises after the reference signal REF, the propagation of the trailing edges of the comparison signal IN to the NAND circuit 14 is delayed behind the NAND circuit 24 by the delayed quantity of a delaying circuit 15, so that the error detection range of the error signal UPB is expanded by the delay quantity of the delay circuit 15 in a direction wherein the reference signal REF is delayed behind the comparison signal IN. Similarly, the error detection range of the error signal DWB is expanded by the delay quantity of a delay circuit 25 in a direction in which the comparison signal IN is delayed behind the reference signal REF.


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Inventors:
Tomokazu Ikeno
Application Number:
JP32792998A
Publication Date:
November 12, 2001
Filing Date:
November 18, 1998
Export Citation:
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Assignee:
NEC
International Classes:
G01R25/00; H03K5/26; H03L7/089; (IPC1-7): H03L7/089; G01R25/00; H03K5/26
Domestic Patent References:
JP62274917A
JP63269822A
JP56169931A
JP9162728A
Attorney, Agent or Firm:
Shigeru Noda