To provide a phase comparator small in the blind sector of a phase difference, excellent in input/output characteristics and capable of being operated stably at a low power supply voltage.

The phase difference of a reference clock signal Fp and the phase difference of a reference clock signal Fr are compared respectively and a 1st phase difference detection signal Pu and a 2nd phase difference detection signal Pd are outputted. A reset circuit 11 is made up of a 2-input NOR circuit 11a and a 3-input NAND circuit 11b to make a delay time of the reset circuit 11 proper thereby improving the input output characteristic of the phase comparator. Furthermore, since the entire phase comparator is configured with 3-input or less logic circuits, the phase comparator is operated stably by employing a lower power supply voltage than that of a conventional phase comparator.