PURPOSE: To enable stable operation even to the input signal with phase difference of zero, by the constitution of the circuit that the S and R input signals of R-SFF are always 1 and 0, when the phase difference between two input signals is zero.

CONSTITUTION: One input of an AND circuit 3 is taken as an error signal, and another input is taken as a signal in which this error signal is delayed by pulse width PWs and the amplitude is inverted with the inverter type delay element 2. One input of an AND circuit 3' is taken as the reference signal, and another input signal is taken as the signal in which it is delayed by the pulse width PWR and the amplitude is inverted. Setting is made by PWSPWR, and one input to the AND circuit 3" is the output of an NAND circuit 9 being both the inputs of the output signal of the circuits 3, 3', and another input is taken as the output signal to the circuit 3'. The output signals of the circuits 3, 3" are taken respectively as the inputs of S and R side of R-SFF5. Thus, when the phase difference between the input signal at the terminals 1 and 7 is zero, S and R signals of R-SFF are always 1 and 0, then the Q output of FF5 is not instable.