Title:
PHASE COMPARATOR
Document Type and Number:
Japanese Patent JPS6418315
Kind Code:
A
Abstract:
PURPOSE: To prevent the effect of unbalanced clock signals by starting a variable pulse at an edge of an input pulse, starting a reference pulse at an edge of a clock pulse and terminating them at an edge of a clock pulse at the end of a succeeding bit cell. CONSTITUTION: Since an FFQ1 is at a low level, its Q output goes to H and since an inverter 62 provides an output of an L level, an OR gate 64 is able to respond to a data pulse. At first the data pulse having a leading edge is given to FFQ1, Q2. The FFQ1 provides a Q output of an H level, an OR gate 60 is active to set an H level to a pump-up signal pulse. The Q output of the FFQ1 goes to L, it is inverted by the inverter 62 and the inverted level drives the OR gate 64 to keep a D input to the FFQ2 to be a high level. When a leading edge of a succeeding clock pulse is received at a C input of the FFQ2, a Q output of the FFQ2 goes to H. The Q output of the FFQ2 activates the OR gate 60 to keep the pumpup signal pulse to be a high level and sets a pump- down pulse to a high level.
Inventors:
BADEIMU BORISU MINUHIN
Application Number:
JP3766688A
Publication Date:
January 23, 1989
Filing Date:
February 22, 1988
Export Citation:
Assignee:
MAGNETIC PERIPHERALS INC
International Classes:
G01R25/00; G01R25/08; H03K17/66; H03L7/089; (IPC1-7): H03L7/08
Attorney, Agent or Firm:
Akira Asamura (2 outside)