Title:
位相比較方法、位相比較回路、及び、PLL回路
Document Type and Number:
Japanese Patent JP3569268
Kind Code:
B2
Abstract:
A phase comparison circuit for generating control voltages for a number of varactors of a phase locked loop (PLL) circuit has been disclosed. According to a particular embodiment, a number of phase difference detection circuits (101, 102 and 103) can be successively activated in response to a set of activation signals to generate output voltage signals (Vtunei). Output voltage signals (Vtunei) can vary according to an elapsed period time, and thus represent a phase difference. Each phase difference detection circuit (101, 102 and 103) can activate a trigger signal (Trg) when an internal voltage signal equals a predetermined value. A main signal (SIG) can be input as an activation signal to a first stage phase difference detection circuit (101). A trigger signal from a first stage phase difference detection circuit (101) can be input as an activation signal to a subsequent stage phase difference detection circuit (102). Phase difference detection circuits (101, 102 and 103) can be deactivated in response to an output signal (out) generated in response to a reference signal (REF), and provide output voltages (Vtunei) which can represent a phase difference between reference signal (REF) and a main signal (SIG).
Inventors:
Glen Cage Murata
Application Number:
JP2002092067A
Publication Date:
September 22, 2004
Filing Date:
March 28, 2002
Export Citation:
Assignee:
nec compound device Co., Ltd.
International Classes:
H03K5/26; H03D13/00; H03L7/087; H03L7/091; H03L7/099; H03L7/18; (IPC1-7): H03L7/091; H03K5/26; H03L7/087; H03L7/099
Foreign References:
| US6150891 |
Attorney, Agent or Firm:
Kiyoshi Inagaki