To provide a phase-compensated clock divider circuit controlling the frequency-divided clock to be always synchronized with a synchronizing signal, and preventing malfunction or delay in operation.

The phase-compensated clock divider circuit is used in a system containing a first component 1 and a second component 2. The first component 1 uses a source clock (first clock) of a predetermined period as an operating clock. The second component 2 uses a frequency division clock obtained by frequency-dividing the source clock as an operating clock in synchronization with the first component 1. The circuit comprises a clock generating means 3 for generating the source clock and outputting it to the first component 1, a dividing means 4 for dividing the source clock and outputting the generated frequency-divided clock to the second component 2, and a synchronous control means 5 for capturing a synchronizing signal generated from the source clock by the first component 1 and outputted to the second component 2 and controlling the dividing means 4 to generate the frequency-divided clock in phase with a point delayed by a predetermined fixed period from a pulse edge of the synchronizing signal.