PURPOSE: To obtain a reproduced clock with a proper phase by detecting the phase of the reproduced clock and a sampled clock so as to control the phase of a comparison signal.

CONSTITUTION: When a data is inputted to a phase detection circuit 14, the data is delayed by delay lines 21a-21c by the phase of π/3 each. A pulse is outputted at the Q output of a D FF 24a depending on the relation of phase of the data and a clock CK. No pulse is generated in the FFs 24a, 24b in the relation between the data and the clock CK'. A pulse is outputted only at the output Q of the FF 24b in the case of a clock CK''. When the frequency of occurrence of the pulses is extracted as a voltage by switches 25a, 25b and integration circuits 26a, 26b, 27a, 27b, the sign of a difference between the output pulses of the D FFs indicates the direction of phase shift and the sign of the sum of them depicts a phase shift quantity. The resulting control voltage is inputted to a phase control circuit 13 to very the phase of a signal Href, thereby matching the phase of the output clock CK of a PLL circuit 11 to an optimum phase with respect to the data.