PURPOSE: To simplify and miniaturize the circuit constitution by providing a phase comparison circuit extracting a phase error quantity, a deciding circuit expressing an optimum sample, an averaging circuit averaging a deciding circuit output signal for each value of log2N (N is a sampling number) bit each and a phase control circuit.

CONSTITUTION: Four sample clocks have phases of 0, π/2, π, 3π/2 with respect to the phase of a reference clock. Suppose that control information and a tentative decision output are coincident, the control information is divided into eight by the MSB and the LSB at each phase region. With the MSBh and the LSBi located at '0', '0', it is discriminated that the phase of the optimum reference clock exists at the region of the phase '0' and with the phase of the optimum reference clock exists at '1', '0', it is discriminated that the optimum reference clock exists at the region of the phase π. With the MSBh and the LSBi located at '1', '1' and '0', '1', the phase depends on shift information (j) and with the shift information (j) at logical '1' and the MSBh and the LSBi at '1', '0', '1', the phase is shifted by π/4 to the left. As a result, the new reference clock phase (f) is shifted to a region where the MSBh and the LSBi are placed at '0', '0'.