PURPOSE: To omit trouble of phase adjustment by allowing two signals to be converted automatically in the completely same phase when there is a phase difference up to maximum ±0.5 bit in the two signals of the same phase transmitted by a digital data transmission system.
CONSTITUTION: A write clock is frequency-divided to 1/2 by a frequency divider circuit 7, one clock divided by 1/2 is inputted to an FF8 and the other clock is inputted to an FF9. The clock obtained by inversion or non-inversion is inputted to a read AND circuit 15 and also inverted by an NOT circuit 13 and the inverted result is inputted to an AND circuit 14. While the clock inputted to the AND circuits 14, 15 is at H level, a data inputted to the AND circuits 14, 15 is read through an OR circuit 16, and an output phase locked to the read clock is obtained. Even if the input data and the write clock are shifted by ±0.5 bit in this way, the same operation as above is performed and the two input data are phase locked automatically.
FUKUSHIMA TAKEO
FURUKAWA TAKAHIRO
TANIDO YOSHIAKI
SATOU KENJI
