To obtain a phase detection circuit whose operating margin is sufficiently ensured.

A data signal D1 to be checked and a clock signal C1 are given to an F/F1 of a D-F/F circuit, a signal C1' resulting from delaying the signal C1 by a delay circuit DL1 and an output signal from the F/F1 are given to an F/F2. Furthermore, the signal D1, an output signal Q1 of the F/F1 and an output signal Q2 of the F/F2 are respectively delayed by three delay circuits DL4, DL3, DL2. An AND circuit AND1 (AND2) ANDs output signals D1' and Q1' (Q1' and Q2') and provides the output of an output signal UP (DOWN) to an adder ADD, which sums the signals UP and DOWN and provides its output signal PDOUT. The phase relation of the signals D1 and C1 such as coincident phase coincidence, phase lead, phase lag is indicated as a change in a form of a duty ratio of the output signal PDOUT. Thus, a problem that the operating margin is deteriorated through high-speed processing can be solved.