Title:
PHASE DETECTION CIRCUIT
Document Type and Number:
Japanese Patent JP3296350
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To obtain a phase detection circuit whose operating margin is sufficiently ensured.
SOLUTION: A data signal D1 to be checked and a clock signal C1 are given to an F/F1 of a D-F/F circuit, a signal C1' resulting from delaying the signal C1 by a delay circuit DL1 and an output signal from the F/F1 are given to an F/F2. Furthermore, the signal D1, an output signal Q1 of the F/F1 and an output signal Q2 of the F/F2 are respectively delayed by three delay circuits DL4, DL3, DL2. An AND circuit AND1 (AND2) ANDs output signals D1' and Q1' (Q1' and Q2') and provides the output of an output signal UP (DOWN) to an adder ADD, which sums the signals UP and DOWN and provides its output signal PDOUT. The phase relation of the signals D1 and C1 such as coincident phase coincidence, phase lead, phase lag is indicated as a change in a form of a duty ratio of the output signal PDOUT. Thus, a problem that the operating margin is deteriorated through high-speed processing can be solved.
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Inventors:
Tetsuo Tateyama
Application Number:
JP33495199A
Publication Date:
June 24, 2002
Filing Date:
November 25, 1999
Export Citation:
Assignee:
NEC
International Classes:
G01R25/00; H03D13/00; H03K5/26; H03L7/089; H04L7/02; H04L7/033; (IPC1-7): H04L7/02; H03K5/26
Domestic Patent References:
| JP200068991A | ||||
| JP7131448A | ||||
| JP58182938A |
Other References:
Ｃｈａｒｌｅｓ Ｒ．Ｈｏｇｇｅ，Ｊｒ．，Ａ Ｓｅｌｆ Ｃｏｒｒｅｃｔｉｎｇ Ｃｌｏｃｋ Ｒｅｃｏｖｅｒｙ Ｃｉｒｃｕｉｔ，ＩＥＥＥ Ｊｏｕｒｎａｌ ｏｆ Ｌｉｇｈｔｗａｖｅ Ｔｅｃｈｎｏｌｏｇｙ，米国，ＩＥＥＥ，Ｖｏｌ．ＬＴ−３，Ｎｏ．６，１３１２−１３１４
Attorney, Agent or Firm:
Takao Maruyama