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Patent Searching and Data


Title:
PHASE DETECTION CIRCUIT
Document Type and Number:
Japanese Patent JPS6238369
Kind Code:
A
Abstract:

PURPOSE: To prevent a large noise outputted in the discontinuous region of the transfer characteristic, by providing a delay circuit or phase shift circuit which changes the phase difference between the reference input and the signal input by a certain amount to reset the operating point into a prescribed range when the phase difference exceeds the upper or lower limit.

CONSTITUTION: If the stationary phase difference between the reference input REF' and the signal input IN applied to the phase detector PD lies near the disconnection part of the transfer characteristic, and the output POUT of the detector PD is in the state of the plus or minus maximum output Vmax, Vmin added with the plus or minus half wave ΔPOUT of the fluctuation component, since the upper limit or lower limit voltage Vth⊕, Vth of a window comparator WC is selected a little smaller than Vmax, or a little larger than Vmin, the comparator WC gives an output to set an FF. Thus, the FF gives an output Q of the H level, which acts as a control signal CTL for a delay circuit DLY to change the delay time for instance from 0 to 0/2. As a result, a normal demodulated output state is obtained. And the FF is reset by the output of an edge detector circuit ED to set the output Q to L.


Inventors:
MURAKAMI KEIICHI
IGARASHI HIROSHI
SHINAMI AKIRA
Application Number:
JP17896285A
Publication Date:
February 19, 1987
Filing Date:
August 14, 1985
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G01R25/00; G01N29/04; G01N29/44; (IPC1-7): G01N29/04; G01R25/00
Attorney, Agent or Firm:
Minoru Aoyagi