To improve detection of phase difference between a digital data signal and a clock signal by providing an index of the phase difference between the clock signal and data signal by comparing a phase signal with the reference signal.
A phase detector 100 consists of data reduction circuits 101a and 101b re-synchronization circuits 102a and 102b, shift register circuits 110 to 112 and XOR gates 105 and 106. A phase difference signal between a reduced data signal generated by the reduction circuit 101b and delayed, re-synchronized and reduced data signal generated by the shift register circuit 110 is generated by the XOR gate 105. The reference signal which is difference between the re-synchronized and reduced data signal outputted from the shift register circuit 111 and the re-synchronized data signal delayed by an amount of A+B generated by the shift register circuit 112 is generated by the XOR gate 106. The difference between the phase difference signal and the reference signal is linearly changed regarding the phase difference between the data signal and the clock signal.
Adrian, Paul Sparks
Foster, Stephen Richard