To provide the phase detector by which an output signal whose spurious signal level is reduced is generated.
The phase detector generates a phase difference signal in response to a phase difference of two applied input signals. The detector has a lead/lag indicator 29 that receives an input signal and a logic block 26 receiving the input signal. The logic block 26 produces an output signal in response to a time delay between corresponding amplitude transition such as respective leading edges of the input signal. The lead/lag indicator 29 records which phase of the two input signals is led and generates an enable signal to lead the output signal from the logic block 26 to one or the other of two output terminals of the phase detector.
|JPS5441050||PHASE SCANNING ARRAY ANTENNA|