Title:
HIGH WIRING-DENSITY CIRCUIT BOARD
Document Type and Number:
Japanese Patent JP3197875
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a method for manufacturing a circuit structure comprising lamination and a plurality of internal flat surfaces of high wiring-density.
SOLUTION: A method of manufacturing a circuit structure comprises a step, where an organic substrate 12 comprising a circuit 14 over it is provided, a step for coating a dielectric film 30 on the organic substrate 12, a step for forming a micro via in the dielectric film 30, a step for sputtering a metal seed layer 20 on the dielectric film 30 and in the micro via, a step for placing a metal layer 22 on the metal seed layer 20, and a step for forming a circuit pattern over it.
Inventors:
Gerald Walter Jones
Ross William Keisler
Vojya Lista Markovich
William John Ruddick
James Warren Wilson
William Earl Wilson
Ross William Keisler
Vojya Lista Markovich
William John Ruddick
James Warren Wilson
William Earl Wilson
Application Number:
JP9499A
Publication Date:
August 13, 2001
Filing Date:
January 04, 1999
Export Citation:
Assignee:
International Business Machines Corporation
International Classes:
H01L21/48; H05K3/38; H05K3/46; H05K3/00; H05K3/16; (IPC1-7): H05K3/46
Domestic Patent References:
| JP745948A | ||||
| JP9331152A | ||||
| JP5218645A |
Other References:
【文献】米国特許5268260(US,A)
Attorney, Agent or Firm:
Hiroshi Sakaguchi (1 person outside)