Title:
PHASE-DIFFERENCE SMOOTHER
Document Type and Number:
Japanese Patent JP2009152682
Kind Code:
A
Abstract:
To reduce a phase error of a multi-phase clock occurring in processes of generation and transmission of the multi-phase clock.
A phase-difference smoother has as same number of phase filter circuits as the number of phases of a multi-phase clock. The phase filter circuit has a weighting means for performing desired weighting on a phase of each clock while inputting a plurality of clocks, having desired phase relationships, of input multi-phase clocks, and an addition means for adding the weighted clocks. The phase-difference smoother outputs clocks output from the phase filter circuits as output multi-phase clocks.
Inventors:
TSUKAMOTO NOBUNARI
EMA HIDETOSHI
EMA HIDETOSHI
Application Number:
JP2007326345A
Publication Date:
July 09, 2009
Filing Date:
December 18, 2007
Export Citation:
Assignee:
RICOH KK
International Classes:
H03K5/15; G06F1/06; H03H17/00; H03H17/02; H03H17/06; H03H17/08; H03L7/00
Domestic Patent References:
| JP2001339280A | 2001-12-07 | |||
| JPH10335991A | 1998-12-18 | |||
| JPH11355262A | 1999-12-24 | |||
| JP2002141785A | 2002-05-17 |
Other References:
JPN6011000437; Ｗ．Ｊ．Ｄａｌｌｙ／Ｊ．Ｗ．Ｐｏｕｌｔｏｎ著 黒田忠広監訳: 「デジタルシステム工学 応用編」 , 20030330, ７５９頁-７６１頁, 丸善株式会社
JPN4006006713; Ｓ．Ｓｉｄｉｒｏｐｏｕｌｏｓ他: '「Ａ Ｓｅｍｉｄｉｇｉｔａｌ Ｄｕａｌ Ｄｅｌａｙ-Ｌｏｃｋｅｄ Ｌｏｏｐ」' ＩＥＥＥ Ｊｏｕｒｎａｌ ｏｆ Ｓｏｌｉｄ-Ｓｔａｔｅ Ｃｉｒｃｕｉｔｓ Ｖｏｌ．３２、Ｎｏ．１１, 199711, Ｐ１６８３-１６９２, ＩＥＥＥ
JPN4006006713; Ｓ．Ｓｉｄｉｒｏｐｏｕｌｏｓ他: '「Ａ Ｓｅｍｉｄｉｇｉｔａｌ Ｄｕａｌ Ｄｅｌａｙ-Ｌｏｃｋｅｄ Ｌｏｏｐ」' ＩＥＥＥ Ｊｏｕｒｎａｌ ｏｆ Ｓｏｌｉｄ-Ｓｔａｔｅ Ｃｉｒｃｕｉｔｓ Ｖｏｌ．３２、Ｎｏ．１１, 199711, Ｐ１６８３-１６９２, ＩＥＥＥ
Attorney, Agent or Firm:
Hitoshi Suzuki
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